Summary and benefits for the attendees
The course discusses Intel’s Many Integrated Core (MIC) architecture. It covers various programming and optimisation techniques for Intel Xeon Phi coprocessors. We will mainly focus on the KNC version of the chip. The hands-on sessions are done on the Intel Xeon Phi based Salomon system at the IT4Innovations National Supercomputing Center.
The afternoon of the second day will be devoted to a plenum session (see below) with invited talks about Intel Xeon Phi experience on Salomon.
The course is developed within the joint German-Czech project CzeBaCCA, as a follow-up of the course of February 2016. This project's workshop HPC in Atmosphere Modelling and Air Related Environmental Hazards will take place at IT4Innovations directly after this course, on February 9, 2017 - see its web page details.
It is organized as a joined event of the National Supercomputing Center IT4Innovations and the Leibniz Supercomputing Centre, which as a PRACE Advanced Training Centre provides high-level training for the Partnership for Advanced Computing in Europe (PRACE).
Level
intermediate
Language
English
Plenum Session
We are pleased to announce an open plenum session (no registration needed) in the afternoon (since 1 pm) on the second day (Wed 8 Februrary). Invited speakers will share with you their MIC experience and best practice recommendations on employing Intel Xeon Phi based systems like Salomon:
- Lukasz Szustak, Roman Wyrzykowski (TU Czestochowa): Exploring the impact of Intel MIC and Intel CPU architectures on accelerating scientific applications
- Jiri Jaros (VUT Brno): Acceleration of the k-Wave toolbox on Xeon Phi
- Milan Jaros (IT4Innovations): Acceleration of Blender Cycles Render Engine using Intel Xeon Phi
- Michal Merta (IT4Innovations): Acceleration of the ESPRESO domain decomposition library
- Jan Zapletal (IT4Innovations):Boundary element quadrature schemes for multi- and many-core architectures
For details of the plenum session, see the attachement below.