Developing efficient HPC applications for the latest CPU architectures with C++ and Fortran (PTC course)

Europe/Prague
207 (VŠB - Technical University Ostrava, IT4Innovations building)

207

VŠB - Technical University Ostrava, IT4Innovations building

Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
Description

Annotation

The course is two-fold: It provides an update on the latest state of the art CPU architectures for HPC and connects them to modern programming in C++ and Fortran.

Covered are all major CPU architectures common in HPC such as Intel (Xeon Scalable Processors), AMD (Epyc) and PowerPC (Power 9). These architectures will be explained in terms of needs for software developers and researchers to utilize their full potential, such as SIMD extensions, cache hierarchies, NUMA configurations, multi-core/-threading, memory bandwidth, throughput, etc.

For each of the addressed architectural properties, techniques and software design patterns are discussed that can be leveraged in modern high-level languages C++ and Fortran. Aside from standardized high-level language features, also compiler specific extensions are highlighted for the latest compilers like GCC/GFortran, LLVM Clang/Flang, IBM XL C++ & Fortran compilers, and Intel C++ & Fortran compilers.

The course will contain up to 50% hands-on exercises covering all topics to practice the techniques and patterns gained.

Level

intermediate - advanced

Language

English

About the tutors

Georg Zitzlsberger formerly worked for Intel Deutschland GmbH (Germany). He has been a Technical Consulting Engineer for Intel(R) Software Development tools for many years before he recently joined IT4Innovations. In his new role as researcher he offers consulting services for Intel Software Development tools and Intel architectures throughout the IT4Innovations network.

Jakub Beránek obtained his Master's Degree in Computer Science and Technology at VŠB - Technical University of Ostrava in 2018. In the same year he joined IT4Innovations as a research assistant at the Advanced Data Analysis and Simulations Laboratory, where he is working on distributed programming models.

Radim Vavřík is a Ph.D. student in Computational Sciences and researcher in the Infrastructure Research Lab at IT4Innovations. He is mainly interested in parallel computing, scalable algorithms design, GPU acceleration and code optimization, and heterogeneous architectures. He worked on hydrological and flood modeling software, and high-performance heterogeneous platform for energy efficient computing. Now he is focused on GPU acceleration of the ESPRESO library, a massively parallel library based on the finite element method (FEM) for engineering applications

Acknowledgements

This course was supported by the PRACE-5IP project – the European Union's Horizon 2020 research and innovation programme under grant
agreement No. 730913.

 

  • Monday, 14 January
    • 09:30 10:00
      Registration/presentation 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 10:00 12:00
      Architecture comparison: Intel Xeon Scalable Processor, AMD Epyc & IBM Power9 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 12:00 13:00
      Lunch 1h Restaurant Pustkovecká Bašta

      Restaurant Pustkovecká Bašta

    • 13:00 14:30
      C++ and Fortran Compilers for Intel & AMD architectures incl. Hands-On 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 14:30 15:00
      Coffee break 30m 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 15:00 16:30
      C++ and Fortran Compilers for IBM architectures incl. Hands-On 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 16:30 17:00
      Q & A 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
  • Tuesday, 15 January
    • 09:00 10:30
      C++ and Fortran design patterns for Intel architectures incl. Hands-On 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 10:30 11:00
      Coffee 30m 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 11:00 12:30
      C++ and Fortran design patterns for AMD architectures incl. Hands-On 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 12:30 13:30
      Lunch 1h Restaurant Pustkovecká Bašta

      Restaurant Pustkovecká Bašta

    • 13:30 15:00
      C++ and Fortran design patterns for IBM architectures incl. Hands-On 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 15:00 15:30
      Q & A 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic