Dec 13 – 14, 2023
HYBRID
Europe/Ljubljana timezone

Annotation

NCC Slovenia and EuroCC Czechia are inviting you to the Training High-Level Synthesis for FPGA. 

Its aim is to demonstrate how to describe, debug, and implement application-specific accelerators on FPGA using the C/C++ language, rather than hardware description languages (e.g., VHDL or Verilog). Through simple examples, participants will learn how to write kernels that can be synthesized on FPGA fabric, transfer data between the host and an FPGA board, and employ various optimization techniques to make the design more efficient in terms of speed and resource utilization. Leveraging the capabilities of HLS, we will develop an accelerator for Cholesky matrix decomposition, utilizing the C/C++ programming language, along with the OpenCL and XRT libraries for development on AMD-Xilinx FPGAs. While the workshop primarily targets AMD-Xilinx FPGA boards, the principles and insights garnered can readily be applied to FPGAs from various other vendors.

Skills to be gained

  • Understanding the operation of heterogeneous computer systems with FPGA.
  • Understanding the FPGA technology.
  • Understanding the concepts of OpenCL and XRT software frameworks and HLS.
  • How to write, translate, and run programs for FPGA.
  • How to use HLS directives for design optimization.

Registration

The registration form is available at https://indico.ijs.si/event/1824/registrations/725/. 

Language

English

Level

Advanced

Prerequisites

Programming language C/C++, usage of a SSH client.

Tutors

Nejc Ilc, Ratko Pilipović

Name:Nejc Ilc
About:https://fri.uni-lj.si/en/about-faculty/employees/nejc-ilc 
Name:Ratko Pilipović
About:https://fri.uni-lj.si/en/about-faculty/employees/ratko-pilipovic 

Organiser

Acknowledgements

This project has received funding from the European High-Performance Computing Joint Undertaking (JU) under grant agreement No 101101903. The JU receives support from the Digital Europe Programme and Germany, Bulgaria, Austria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Greece, Hungary, Ireland, Italy, Lithuania, Latvia, Poland, Portugal, Romania, Slovenia, Spain, Sweden, France, Netherlands, Belgium, Luxembourg, Slovakia, Norway, Türkiye, Republic of North Macedonia, Iceland, Montenegro, Serbia. This project has received funding from the Ministry of Education, Youth, and Sports of the Czech Republic.

This course was supported by the Ministry of Education, Youth and Sports of the Czech Republic through the e-INFRA CZ (ID:90254).

Starts
Ends
Europe/Ljubljana
HYBRID

Registration

The registration form is available at https://indico.ijs.si/event/1824/registrations/725/. 

More course information can be found at https://indico.ijs.si/event/1824/. 

Target audience

Researchers, engineers, students, and anyone interested in accelerating algorithm performance using FPGA technology.

Location

University of Ljubljana, Faculty of computer and information science, Večna pot 113, Ljubljana      Room: TBD 

Maximum number of participants 

10

Duration

13.12.2023 - 14.12.2023, hours TBD