Intel MIC Programming Workshop (IT4I training)

Europe/Prague
207 (VŠB - Technical University Ostrava, IT4Innovations building)

207

VŠB - Technical University Ostrava, IT4Innovations building

Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
Description

Annotation

Fortran remains widely used in high-performance computing (HPC), but most users describe their programming skills as self-taught and most use older language versions. The increasing compiler support for modern Fortran makes the time ripe to teach new language features that target HPC. We will teach single-program, multiple-data (SPMD) programming with Fortran 2008 coarrays. We also introduce Fortran's loop concurrency and pure procedure features and demonstrate their use in asynchronous expression evaluation for partial differential equation (PDE) solvers. We incorporate other language features, including object-oriented (OO) programming, when they support parallel  programming pedagogy. In particular, we

The course discusses Intel’s new Many Integrated Core (MIC) architecture. It covers various programming and optimisation techniques for Intel  Xeon Phi coprocessors. The hands-on sessions are done on the new Intel Xeon Phi based Salomon system at the Czech National Supercomputing Centre IT4Innovations.

The course is developed within the joint German-Czech Republic project CzeBaCCA. A one-day workshop on Seismic Simulation Software of this project will take place at IT4Innovations directly after this course, on February 5, 2016 - see its web page for details.

OO design patterns for hybrid CPU/GPU calculations in the Parallel Sparse Basic Linear Algebra Subroutines (PSBLAS) library.

Level

Basic/Intermediate

Language

English

About the tutor(s)

Volker Weinberg studied physics at the Ludwig Maximilian University of Munich and later worked at the research centre DESY. He received his PhD from the Free University of Berlin for his studies in the field of lattice QCD. Since 2008 he is working in the HPC group at the Leibniz Supercomputing Centre and is responsible for HPC and PATC (PRACE Advanced Training Centre) courses at LRZ, new programming languages and the Intel Xeon Phi based system SuperMIC. Within PRACE-4IP he took over the leadership to create Best Practice Guides for new architectures and systems.

Momme Allalen received his Ph.D in theoretical Physics from the University of Osnabrück in 2006. He worked in the field of molecular magnetics through modelling techniques such as the exact numerical diagonalisation of the Heisenberg model. He joined the Leibniz Computing Centre (LRZ) in 2007 working in the High Performance Computing group. His tasks include user support, optimisation and parallelisation of scientific application codes, and benchmarking for characterising and evaluating the performance of high-end supercomputers. His research interests are various aspects of parallel computing and new programming languages and paradigms.

Branislav Jansik has obtained his PhD in computational chemistry at Royal Institute of Technology, Sweden in 2004. He took postdoctoral position at IPCF, Consiglio Niazionale delle Ricerche, Italy,  to carry on development and applications of high performance computational methods for molecular optical properties. Since 2006 he worked on development of highly parallel optimization methods in the domain of electronic structure theory at Aarhus University, Denmark. In 2012 he joined IT4Innovations, the Czech national supercomputing center as a head of supercomputing services. He published over 35 papers and co-authored the DALTON electronic structure theory code

Acknowledgements

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TUMLRZIT4I

  • Wednesday, 3 February
    • Registration 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • Welcome 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • Salomon intro (Jansik) 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 11:30
      Lunch break
    • Overview of the Intel MIC architecture and programming models, native mode programming (Allalen/Weinberg) 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 14:30
      Coffee break 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • OpenMP and offloading, Part 1 (Weinberg) 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 16:30
      Coffee break 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • OpenMP and offloading, Part 2 (Weinberg) 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
      • 17:00
        Coffee break
  • Thursday, 4 February
    • MPI (Weinberg) 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 10:30
      Coffee break 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • MKL (Allalen) 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic
    • 12:45
      Lunch break
    • Vectorisation and basic Xeon Phi performance optimisation (Allalen/Weinberg) 207

      207

      VŠB - Technical University Ostrava, IT4Innovations building

      Studentská 6231/1B 708 33 Ostrava–Poruba Czech Republic